Part Number Hot Search : 
LRS1383C 1D44D PJS6815 BA9741F 07005 LTC2271 2SA1209T BU2525A
Product Description
Full Text Search
 

To Download MX25L1605D Datasheet File
  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
　
 

  Datasheet File OCR Text:
  1 16m-bit [x 1 / x 2] cmos serial flash 32m-bit [x 1 / x 2] cmos serial flash 64m-bit [x 1 / x 2] cmos serial flash features general ? serial peripheral interface compatible -- mode 0 and mode 3 ? 16m:16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two i/o read mode) structure 32m:33,554,432 x 1 bit structure or 16,772,216 x 2 bits (two i/o read mode) structure 64m:67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two i/o read mode) structure ? 512 equal sectors with 4k byte each (16mb) 1024 equal sectors with 4k byte each (32mb) 2048 equal sectors with 4k byte each (64mb) - any sector can be erased individually ? 32 equal blocks with 64k byte each (16mb) 64 equal blocks with 64k byte each (32mb) 128 equal blocks with 64k byte each (64mb) - any block can be erased individually ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program operations ? latch-up protected to 100ma from -1v to vcc +1v ? low vcc write inhibit is from 1.5v to 2.5v performance ? high performance - fast access time: 86mhz serial clock (15pf + 1ttl load) and 66mhz serial clock (30pf + 1ttl load) - serial clock of two i/o read mode : 50mhz (15pf + ttl load), which is equivalent to 100mhz - fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - byte program time: 9us (typical) - continuously program mode (automatically increase address under word program mode) - fast erase time: 60ms(typ.) /sector (4k-byte per sector) ; 0.7s(typ.) /block (64k-byte per block); 14s(typ.) /chip for 16mb, 25s(typ.) for 32mb, and 50s(typ.) for 64mb ? low power consumption - low active read current: 25ma(max.) at 86mhz, 20ma(max.) at 66mhz and 10ma(max.) at 33mhz - low active programming current: 20ma (max.) - low active erase current: 20ma (max.) - low standby current: 20ua (max.) - deep power-down mode 1ua (typical) ? typical 100,000 erase/program cycles software features ? input data format - 1-byte command code ? advanced security features - block lock protection the bp0-bp3 status bit defines the size of the area to be software protection against program and erase instructions - additional 512-bit secured otp for unique identifier ? auto erase and auto program algorithm - automatically erases and verifies data at selected sector - automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programed should have page in the erased state first) p/n: pm1290 rev. 1.4, oct. 01, 2008 MX25L1605D mx25l3205d mx25l6405d
2 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 ? status register feature ? electronic identification - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - both rems and rems2 commands for 1-byte manufacturer id and 1-byte device id hardware features ? sclk input - serial clock input ? si input - serial data input ? so output - serial data output ? wp#/acc pin - hardware write protection and program/erase acceleration ? hold# pin - pause the chip without diselecting the chip ? package - 16-pin sop (300mil) - 8-land wson (8x6mm or 6x5mm) - 8-pin sop (200mil, 150mil) - 8-pin pdip (300mil) - 8-land uson (4x4mm) - all pb-free devices are rohs compliant alternative ? security serial flash (mx25l1615d/mx25l3215d/mx25l6415d) may provides additional protection features for op- tion. the datasheet is provided under nda. general description the MX25L1605D are 16,777,216 bit serial flash memory, which is configured as 2,097,152 x 8 internally. when it is in two i/o read mode, the structure becomes 8,388,608 bits x 2. the mx25l3205d are 33,554,432 bit serial flash memory, which is configured as 4,194,304 x 8 internally. when it is in two i/o read mode, the structure becomes 16,772,216 bits x 2. the mx25l6405d are 67,108,864 bit serial flash memory, which is configured as 8,388,608 x 8 internally. when it is in two i/o read mode, the structure becomes 33,554,432 bits x 2. (please refer to the "two i/o read mode" section). the MX25L1605D/3205d/6405d feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. when it is in two i/o read mode, the si pin and so pin become sio0 pin and sio1 pin for address/dummy bits input and data output. the MX25L1605D/3205d/6405d provides sequential read operation on whole chip. after program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. program command is executed on byte basis, or page (256 bytes) basis, or word basis for continuously program mode, and erase command is executes on sector (4k-byte), or block (64k-byte), or whole chip basis.
3 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 table 1. additional feature comparison to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. advanced security features enhance the protection and security functions, please see security features section for more details. when the device is not in operation and cs# is high, it is put in standby mode and draws less than 20ua dc current. the MX25L1605D/3205d/6405d utilizes mxic's proprietary memory cell, which reliably stores memory contents even after typical 100,000 program and erase cycles. read performance MX25L1605D v v v 14 (hex) c2 14 (hex) (if add=0) c2 14 (hex) (if add=0) c2 20 15 (hex) identifier protection and security featu- res part name additional device id (command : ef hex) rdid (command: 9f hex) 512-bit secured otp 2 i/o read (50mhz) device id (command : ab hex) device id (command : 90 hex) flexible block protection ( bp0-bp3 ) mx25l3205d v v v 15 (hex) c2 15 (hex) (if add=0) c2 15 (hex) (if add=0) c2 20 16 (hex) mx25l6405d v v v 16 (hex) c2 16 (hex) (if add=0) c2 16 (hex) (if add=0) c2 20 17 (hex)
4 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 pin configurations symbol description cs# chip select si/sio0 serial data input (for 1 x i/o)/ serial data input & output (for 2xi/o read mode) so/sio1 serial data output (for 1 x i/o)/ serial data input & output (for 2xi/o read mode) sclk clock input wp#/acc w rite protection: connect to gnd ; 9.5~10.5v for program/erase acceleration: connect to 9.5~10.5v hold# hold, to pause the device without deselecting the device vcc + 3.3v power supply gnd ground pin description 16-pin sop (300mil) 8-land wson (8x6mm, 6x5mm), uson (4x4mm) 8-pin sop (200mil, 150mil) package options 16m 32m 64m 150mil 8-sop v 200mil 8-sop v v 300mil 16-sop v v v 300mil 8-pdip v v 6x5mm wson v v 8x6mm wson v 4x4mm uson v v 1 2 3 4 5 6 7 8 hold# vcc nc nc nc nc cs# so/sio1 16 15 14 13 12 11 10 9 sclk si/sio0 nc nc nc nc gnd wp#/acc 1 2 3 4 cs# so/sio1 wp#/acc gnd vcc hold# sclk si/sio0 8 7 6 5 1 2 3 4 cs# so/sio1 wp#/acc gnd 8 7 6 5 vcc hold# sclk si/sio0 1 2 3 4 cs# so/sio1 wp#/acc gnd 8 7 6 5 vcc hold# sclk si/sio0 8-pin pdip (300mil)
5 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si/sio0 sclk clock generator state machine mode logic sense amplifier hv generator output buffer so/sio1 cs#, wp#/acc, hold#
6 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 data protection the MX25L1605D/3205d/6405d is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically resets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transition or system noise. ? power-on reset and tpuw: to avoid sudden power switch by system power supply transition, the power-on reset and tpuw (internal timer) may protect the flash. ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - write disable (wrdi) command completion - write status register (wrsr) command completion - page program (pp) command completion - continuously program mode (cp) instruction completion - sector erase (se) command completion - block erase (be) command completion - chip erase (ce) command completion - write read-lock bit (wrlb) instruction completion ? deep power down mode: by entering deep power down mode, the flash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic signature command (res). ? advanced security features: there are some protection and securuity features which protect content from inadvertent write and hostile access. i. block lock protection - the software protected mode (spm) use (bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only. the proected area definition is shown as table of "protected area sizes", the protected areas are more flexible which may protect various area by setting value of bp0-bp3 bits. please refer to table of "protected area sizes". - the hardware proteced mode (hpm) use wp#/acc to protect the (bp3, bp2, bp1, bp0) bits and srwd bit.
7 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 ii. additional 512-bit secured otp for unique identifier: to provide 512-bit one-time program area for setting device unique serial number - which may be set by factory or system customer. please refer to table 3. 512-bit secured otp definition. - security register bit 0 indicates whether the chip is locked by factory or not. - to program the 512-bit secured otp by entering 512-bit secured otp mode (with enso command), and going through normal program procedure, and then exiting 512-bit secured otp mode by writing exso command. - customer may lock-down the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to table of "security register definition" for security register bit definition and table of "512-bit secured otp definition" for address range definition. - note: once lock-down whatever by factory or customer, it cannot be changed any more. while in 512-bit secured otp mode, array access is not allowed. table 3. 512-bit secured otp definition table 2. protected area sizes address range size standard customer lock factory lock xxxx00~xxxx0f 128-bit esn (electrical serial number) determined by customer xxxx10~xxxx3f 384-bit n/a bp3 bp2 bp1 bp0 16mb 000 00 ( none ) 000 11 ( 1block, block 31th ) 001 02 ( 2blocks, block 30th-31th ) 001 13 ( 4blocks, block 28th-31th ) 010 04 ( 8blocks, block 24th-31th ) 010 15 ( 16blocks, block 16th-31th ) 011 06 ( 32blocks, all ) 011 17 ( 32blocks, all ) 100 08 ( 32blocks, all ) 100 19 ( 32blocks, all ) 101 010 ( 16blocks, block 0th-15th ) 1 0 1 1 11(24blocks, block 0th-23th) 110 012 ( 28blocks, block 0th-27th ) 110 113 ( 30blocks, block 0th-29th ) 111 014 ( 31blocks, block 0th-30th ) 111 115 ( 32blocks, all ) status bit protect level 32mb 64mb 0 ( none ) 1 ( 1block, block 63th ) 2 ( 2blocks, block 62th-63th ) 3 ( 4blocks, block 60th-63th ) 4 ( 8blocks, block 56th-63th ) 5 ( 16blocks, block 48th-63th ) 6 ( 32blocks, block 32th-63th ) 7 ( 64blocks, all ) 8 ( 64blocks, all ) 9(32blocks, block 0th-31th) 10 ( 48blocks, block 0th-47th ) 11(56blocks, block 0th-55th) 12 ( 60blocks, block 0th-59th ) 13 ( 62blocks, block 0th-61th ) 14 ( 63blocks, block 0th-62th ) 15 ( 64blocks, all ) 0 ( none ) 1(2blocks, block 126th-127th) 2 ( 4blocks, block 124th-127th ) 3 ( 8blocks, block 120th-127th ) 4 ( 16blocks, block 112th-127th ) 5 ( 32blocks, block 96th-127th ) 6(64blocks,block 64th-127th) 7 ( 128blocks, all ) 8 ( 128blocks, all ) 9(64blocks, block 0th-63th) 10 ( 96blocks, block 0th-95th ) 11(112blocks, block 0th-111th) 12 ( 120blocks, block 0th-119th ) 13 ( 124blocks, block 0th-123th ) 14 ( 126blocks, block 0th-125th ) 15 ( 128blocks, all )
8 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 hold features hold# pin signal goes low to hold any serial communications with the device. the hold feature will not stop the operation of write status register, programming, or erasing in progress. the operation of hold requires chip select(cs#) keeping low and starts on falling edge of hold# pin signal while serial clock (sclk) signal is being low (if serial clock signal is not being low, hold operation will not start until serial clock signal being low). the hold condition ends on the rising edge of hold# pin signal while serial clock(sclk) signal is being low( if serial clock signal is not being low, hold operation will not end until serial clock being low), see figure 1. figure 1. hold condition operation program/erase acceleration to activate the program/erase acceleration function requires acc pin connecting to 9.5~10.5v voltage (see figure 2), and then to be followed by the normal program/erase process. by utilizing the program/erase acceleration operation, the performances are improved as shown on table of "erase and program performace". after power-up ready, it should wait 10ms at least to apply vhh(9.5~10.5v) on the wp#/acc pin. figure 2. accelerated program timing diagram note: tvhh (vhh rise and fall time) min. 250ns hold# cs# sclk hold condition (standard) hold condition (non-standard) the serial data output (so) is high impedance, both serial data input (si) and serial clock (sclk) are don't care during the hold operation. if chip select (cs#) drives high during hold operation, it will reset the internal logic of the device. to re-start communication with chip, the hold# must be at high and cs# must be at low. acc 9.5~10.5v t vhh v hh v il or v ih v il or v ih t vhh
9 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 table 4. command definition command (byte) wren (write enable) wrdi (write disable) rdid (read identification ) rdsr (read status re g ister ) wrsr (write status re g ister ) read (read data) fast read (fast read data ) 2read (2 x i/o read command) note1 se (sector erase) 1st b y t e 06 (hex) 04 (hex) 9f (hex) 05 (hex) 01 ( hex ) 03 (hex) 0b ( hex ) bb ( hex ) 20 ( hex ) 2nd byte ad1 ad1 add ( 2 ) ad1 3rd byte ad2 ad2 add(2) & dumm y( 2 ) ad2 4th byte ad3 ad3 ad3 5th byte action sets the (wel) write enable latch bit resets the (wel) write enable latch bit outputs jedec id: 1-byte manufactur er id & 2- byte device id to read out the values of the status register to write new values to the status register n bytes read out until cs# goes high n bytes read out until cs# goes high n bytes read out by 2 x i/o until cs# goes high to erase the selected sector note 1: the count base is 4-bit for add ( 2 ) and dumm y( 2 ) because of 2 x i/o. and the msb is on si/sio0 which is different from 1 x i/o condition command (byte) be (block erase) ce (chip erase) pp (page program) cp (continuo- usly program mode) dp (deep power down) rdp (release from deep power down) res (read electronic id) rems (read electronic manufactu- rer & device id ) rems2 (read id for 2x i/o mode) 1st byte d8 (hex) 60 or c7 ( hex ) 02 (hex) ad (hex) b9 (hex) ab (hex) ab (hex) 90 (hex) ef (hex) 2nd byte ad1 ad1 ad1 x x x 3rd b y t e ad2 ad2 ad2 x x x 4th byte ad3 ad3 ad3 x add(note 2 ) add(note 2 ) 5th byte action to erase the selected block to erase whole chip to program the selected page continously program whole chip, the address is automatica ll y increas e enters deep power down mode release from deep power down mode to read out 1-byte device id outout the manufactu- rer id & device id output the manufactu- rer id & device id note 2: add=00h will output the manufacturer id first and add=01h will output device id first note 3: it is not recommoded to adopt any other code not in the command definition table, which will potentially enter the hidden mode. command (byte) enso (enter secured otp) exso (exit secured otp) rdscur (read security register) wrscur (write security register) esry (enable so to output ry/by# ) dsry (disable so to output ry/by# ) 1st b y t e b1 ( hex ) c1 (hex) 2b ( hex ) 2f (hex) 70 (hex) 80 (hex) 2nd byte 3rd b y t e 4th byte 5th byte action to enter the 512-bit secured otp mode to exit the 512-bit secured otp mode to read value of security register to set the lock-down bit as "1" (once lock- down, cannot be u p dated ) to enable so to output ry/by# during cp mode to disable so to output ry/by# during cp mode dumm y
10 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 table 5-1. memory organization (16mb) block 31 511 . . . . . . . . . 496 1ff000h 1f0000h 1fffffh 1f0fffh sector address range 30 495 . . . . . . . . . 480 1ef000h 1e0000h 1effffh 1e0fffh 29 479 . . . . . . . . . 464 1df000h 1d0000h 1dffffh 1d0fffh 28 463 . . . . . . . . . 448 1cf000h 1c0000h 1cffffh 1c0fffh 27 447 . . . . . . . . . 432 1bf000h 1b0000h 1bffffh 1b0fffh 26 431 . . . . . . . . . 416 1af000h 1a0000h 1affffh 1a0fffh 25 415 . . . . . . . . . 400 19f000h 190000h 19ffffh 190fffh 24 399 . . . . . . . . . 384 18f000h 180000h 18ffffh 180fffh 23 383 . . . . . . . . . 368 17f000h 170000h 17ffffh 170fffh 22 367 . . . . . . . . . 352 16f000h 160000h 16ffffh 160fffh 21 351 . . . . . . . . . 336 15f000h 150000h 15ffffh 150fffh 20 335 . . . . . . . . . 320 14f000h 140000h 14ffffh 140fffh 19 319 . . . . . . . . . 304 13f000h 130000h 13ffffh 130fffh 18 303 . . . . . . . . . 288 12f000h 120000h 12ffffh 120fffh 17 287 . . . . . . . . . 272 11f000h 110000h 11ffffh 110fffh 16 271 . . . . . . . . . 256 10f000h 100000h 10ffffh 100fffh block 15 255 . . . . . . . . . 240 0ff000h 0f0000h 0fffffh 0f0fffh sector address range 14 239 . . . . . . . . . 224 0ef000h 0e0000h 0effffh 0e0fffh 13 223 . . . . . . . . . 208 0df000h 0d0000h 0dffffh 0d0fffh 12 207 . . . . . . . . . 192 0cf000h 0c0000h 0cffffh 0c0fffh 11 191 . . . . . . . . . 176 0bf000h 0b0000h 0bffffh 0b0fffh 10 175 . . . . . . . . . 160 0af000h 0a0000h 0affffh 0a0fffh 9 159 . . . . . . . . . 144 09f000h 090000h 09ffffh 090fffh 8 143 . . . . . . . . . 128 08f000h 080000h 08ffffh 080fffh 7 127 . . . . . . . . . 112 07f000h 070000h 07ffffh 070fffh 6 111 . . . . . . . . . 96 06f000h 060000h 06ffffh 060fffh 5 95 . . . . . . . . . 80 05f000h 050000h 05ffffh 050fffh 4 79 . . . . . . . . . 64 04f000h 040000h 04ffffh 040fffh 3 63 . . . . . . . . . 48 03f000h 030000h 03ffffh 030fffh 2 47 . . . . . . . . . 32 02f000h 020000h 02ffffh 020fffh 1 31 . . . . . . . . . 16 01f000h 010000h 01ffffh 010fffh 0 15 . . . . . . . . . 4 00f000h 004000h 00ffffh 004fffh 3 003000h 003fffh 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh
11 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 table 5-2. memory organization (32mb) block 63 1023 . . . . . . . . . 1008 3ff000h 3f0000h 3fffffh 3f0fffh sector address range 62 1007 . . . . . . . . . 992 3ef000h 3e0000h 3effffh 3e0fffh 61 991 . . . . . . . . . 976 3df000h 3d0000h 3dffffh 3d0fffh 60 975 . . . . . . . . . 960 3cf000h 3c0000h 3cffffh 3c0fffh 59 959 . . . . . . . . . 944 3bf000h 3b0000h 3bffffh 3b0fffh 58 943 . . . . . . . . . 928 3af000h 3a0000h 3affffh 3a0fffh 57 927 . . . . . . . . . 912 39f000h 390000h 39ffffh 390fffh 56 911 . . . . . . . . . 896 38f000h 380000h 38ffffh 380fffh 55 895 . . . . . . . . . 880 37f000h 370000h 37ffffh 370fffh 54 879 . . . . . . . . . 864 36f000h 360000h 36ffffh 360fffh 53 863 . . . . . . . . . 848 35f000h 350000h 35ffffh 350fffh 52 847 . . . . . . . . . 832 34f000h 340000h 34ffffh 340fffh 51 831 . . . . . . . . . 816 33f000h 330000h 33ffffh 330fffh 50 815 . . . . . . . . . 800 32f000h 320000h 32ffffh 320fffh 49 799 . . . . . . . . . 784 31f000h 310000h 31ffffh 310fffh 48 783 . . . . . . . . . 768 30f000h 300000h 30ffffh 300fffh block 47 767 . . . . . . . . . 752 2ff000h 2f0000h 2fffffh 2f0fffh sector address range 46 751 . . . . . . . . . 736 2ef000h 2e0000h 2effffh 2e0fffh 45 735 . . . . . . . . . 720 2df000h 2d0000h 2dffffh 2d0fffh 44 719 . . . . . . . . . 704 2cf000h 2c0000h 2cffffh 2c0fffh 43 703 . . . . . . . . . 688 2bf000h 2b0000h 2bffffh 2b0fffh 42 687 . . . . . . . . . 672 2af000h 2a0000h 2affffh 2a0fffh 41 671 . . . . . . . . . 656 29f000h 290000h 29ffffh 290fffh 40 655 . . . . . . . . . 640 28f000h 280000h 28ffffh 280fffh 39 639 . . . . . . . . . 624 27f000h 270000h 27ffffh 270fffh 38 623 . . . . . . . . . 608 26f000h 260000h 26ffffh 260fffh 37 607 . . . . . . . . . 592 25f000h 250000h 25ffffh 250fffh 36 591 . . . . . . . . . 576 24f000h 240000h 24ffffh 240fffh 35 575 . . . . . . . . . 560 23f000h 230000h 23ffffh 230fffh 34 559 . . . . . . . . . 544 22f000h 220000h 22ffffh 220fffh 33 543 . . . . . . . . . 528 21f000h 210000h 21ffffh 210fffh 32 527 . . . . . . . . . 512 20f000h 200000h 20ffffh 200fffh
12 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 block 31 511 . . . . . . . . . 496 1ff000h 1f0000h 1fffffh 1f0fffh sector address range 30 495 . . . . . . . . . 480 1ef000h 1e0000h 1effffh 1e0fffh 29 479 . . . . . . . . . 464 1df000h 1d0000h 1dffffh 1d0fffh 28 463 . . . . . . . . . 448 1cf000h 1c0000h 1cffffh 1c0fffh 27 447 . . . . . . . . . 432 1bf000h 1b0000h 1bffffh 1b0fffh 26 431 . . . . . . . . . 416 1af000h 1a0000h 1affffh 1a0fffh 25 415 . . . . . . . . . 400 19f000h 190000h 19ffffh 190fffh 24 399 . . . . . . . . . 384 18f000h 180000h 18ffffh 180fffh 23 383 . . . . . . . . . 368 17f000h 170000h 17ffffh 170fffh 22 367 . . . . . . . . . 352 16f000h 160000h 16ffffh 160fffh 21 351 . . . . . . . . . 336 15f000h 150000h 15ffffh 150fffh 20 335 . . . . . . . . . 320 14f000h 140000h 14ffffh 140fffh 19 319 . . . . . . . . . 304 13f000h 130000h 13ffffh 130fffh 18 303 . . . . . . . . . 288 12f000h 120000h 12ffffh 120fffh 17 287 . . . . . . . . . 272 11f000h 110000h 11ffffh 110fffh 16 271 . . . . . . . . . 256 10f000h 100000h 10ffffh 100fffh block 15 255 . . . . . . . . . 240 0ff000h 0f0000h 0fffffh 0f0fffh sector address range 14 239 . . . . . . . . . 224 0ef000h 0e0000h 0effffh 0e0fffh 13 223 . . . . . . . . . 208 0df000h 0d0000h 0dffffh 0d0fffh 12 207 . . . . . . . . . 192 0cf000h 0c0000h 0cffffh 0c0fffh 11 191 . . . . . . . . . 176 0bf000h 0b0000h 0bffffh 0b0fffh 10 175 . . . . . . . . . 160 0af000h 0a0000h 0affffh 0a0fffh 9 159 . . . . . . . . . 144 09f000h 090000h 09ffffh 090fffh 8 143 . . . . . . . . . 128 08f000h 080000h 08ffffh 080fffh 7 127 . . . . . . . . . 112 07f000h 070000h 07ffffh 070fffh 6 111 . . . . . . . . . 96 06f000h 060000h 06ffffh 060fffh 5 95 . . . . . . . . . 80 05f000h 050000h 05ffffh 050fffh 4 79 . . . . . . . . . 64 04f000h 040000h 04ffffh 040fffh 3 63 . . . . . . . . . 48 03f000h 030000h 03ffffh 030fffh 2 47 . . . . . . . . . 32 02f000h 020000h 02ffffh 020fffh 1 31 . . . . . . . . . 16 01f000h 010000h 01ffffh 010fffh 0 15 . . . . . . . . . 4 00f000h 004000h 00ffffh 004fffh 3 003000h 003fffh 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh
13 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 table 5-3. memory organization (64mb) block 127 2047 . . . . . . . . . 2032 7ff000h 7f0000h 7fffffh 7f0fffh sector address range 126 2031 . . . . . . . . . 2016 7ef000h 7e0000h 7effffh 7e0fffh 125 2015 . . . . . . . . . 2000 7df000h 7d0000h 7dffffh 7d0fffh 124 1999 . . . . . . . . . 1984 7cf000h 7c0000h 7cffffh 7c0fffh 123 1983 . . . . . . . . . 1968 7bf000h 7b0000h 7bffffh 7b0fffh 122 1967 . . . . . . . . . 1952 7af000h 7a0000h 7affffh 7a0fffh 121 1951 . . . . . . . . . 1936 79f000h 790000h 79ffffh 790fffh 120 1935 . . . . . . . . . 1920 78f000h 780000h 78ffffh 780fffh 119 1919 . . . . . . . . . 1904 77f000h 770000h 77ffffh 770fffh 118 1903 . . . . . . . . . 1888 76f000h 760000h 76ffffh 760fffh 117 1887 . . . . . . . . . 1872 75f000h 750000h 75ffffh 750fffh 116 1871 . . . . . . . . . 1856 74f000h 740000h 74ffffh 740fffh 115 1855 . . . . . . . . . 1840 73f000h 730000h 73ffffh 730fffh 114 1839 . . . . . . . . . 1824 72f000h 720000h 72ffffh 720fffh 113 1823 . . . . . . . . . 1808 71f000h 710000h 71ffffh 710fffh 112 1807 . . . . . . . . . 1792 70f000h 700000h 70ffffh 700fffh block 111 1791 . . . . . . . . . 1776 6ff000h 6f0000h 6fffffh 6f0fffh sector address range 110 1775 . . . . . . . . . 1760 6ef000h 6e0000h 6effffh 6e0fffh 109 1759 . . . . . . . . . 1744 6df000h 6d0000h 6dffffh 6d0fffh 108 1743 . . . . . . . . . 1728 6cf000h 6c0000h 6cffffh 6c0fffh 107 1727 . . . . . . . . . 1712 6bf000h 6b0000h 6bffffh 6b0fffh 106 1711 . . . . . . . . . 1696 6af000h 6a0000h 6affffh 6a0fffh 105 1695 . . . . . . . . . 1680 69f000h 690000h 69ffffh 690fffh 104 1679 . . . . . . . . . 1664 68f000h 680000h 68ffffh 680fffh 103 1663 . . . . . . . . . 1648 67f000h 670000h 67ffffh 670fffh 102 1647 . . . . . . . . . 1632 66f000h 660000h 66ffffh 660fffh 101 1631 . . . . . . . . . 1616 65f000h 650000h 65ffffh 650fffh 100 1615 . . . . . . . . . 1600 64f000h 640000h 64ffffh 640fffh 99 1599 . . . . . . . . . 1584 63f000h 630000h 63ffffh 630fffh 98 1583 . . . . . . . . . 1568 62f000h 620000h 62ffffh 620fffh 97 1567 . . . . . . . . . 1552 61f000h 610000h 61ffffh 610fffh 96 1551 . . . . . . . . . 1536 60f000h 600000h 60ffffh 600fffh
14 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 block 95 1535 . . . . . . . . . 1520 5ff000h 5f0000h 5fffffh 5f0fffh sector address range 94 1519 . . . . . . . . . 1504 5ef000h 5e0000h 5effffh 5e0fffh 93 1503 . . . . . . . . . 1488 5df000h 5d0000h 5dffffh 5d0fffh 92 1487 . . . . . . . . . 1472 5cf000h 5c0000h 5cffffh 5c0fffh 91 1471 . . . . . . . . . 1456 5bf000h 5b0000h 5bffffh 5b0fffh 90 1455 . . . . . . . . . 1440 5af000h 5a0000h 5affffh 5a0fffh 89 1439 . . . . . . . . . 1424 59f000h 590000h 59ffffh 590fffh 88 1423 . . . . . . . . . 1408 58f000h 580000h 58ffffh 580fffh 87 1407 . . . . . . . . . 1392 57f000h 570000h 57ffffh 570fffh 86 1391 . . . . . . . . . 1376 56f000h 560000h 56ffffh 560fffh 85 1375 . . . . . . . . . 1360 55f000h 550000h 55ffffh 550fffh 84 1359 . . . . . . . . . 1344 54f000h 540000h 54ffffh 540fffh 83 1343 . . . . . . . . . 1328 53f000h 530000h 53ffffh 530fffh 82 1327 . . . . . . . . . 1312 52f000h 520000h 52ffffh 520fffh 81 1311 . . . . . . . . . 1296 51f000h 510000h 51ffffh 510fffh 80 1295 . . . . . . . . . 1280 50f000h 500000h 50ffffh 500fffh block 79 1279 . . . . . . . . . 1264 4ff000h 4f0000h 4fffffh 4f0fffh sector address range 78 1263 . . . . . . . . . 1248 4ef000h 4e0000h 4effffh 4e0fffh 77 1247 . . . . . . . . . 1232 4df000h 4d0000h 4dffffh 4d0fffh 76 1231 . . . . . . . . . 1216 4cf000h 4c0000h 4cffffh 4c0fffh 75 1215 . . . . . . . . . 1200 4bf000h 4b0000h 4bffffh 4b0fffh 74 1119 . . . . . . . . . 1184 4af000h 4a0000h 4affffh 4a0fffh 73 1183 . . . . . . . . . 1168 49f000h 490000h 49ffffh 490fffh 72 1167 . . . . . . . . . 1152 48f000h 480000h 48ffffh 480fffh 71 1151 . . . . . . . . . 1136 47f000h 470000h 47ffffh 470fffh 70 1135 . . . . . . . . . 1120 46f000h 460000h 46ffffh 460fffh 69 1119 . . . . . . . . . 1104 45f000h 450000h 45ffffh 450fffh 68 1103 . . . . . . . . . 1088 44f000h 440000h 44ffffh 440fffh 67 1087 . . . . . . . . . 1072 43f000h 430000h 43ffffh 430fffh 66 1071 . . . . . . . . . 1056 42f000h 420000h 42ffffh 420fffh 65 1055 . . . . . . . . . 1040 41f000h 410000h 41ffffh 410fffh 64 1039 . . . . . . . . . 1024 40f000h 400000h 40ffffh 400fffh
15 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 block 63 1023 . . . . . . . . . 1008 3ff000h 3f0000h 3fffffh 3f0fffh sector address range 62 1007 . . . . . . . . . 992 3ef000h 3e0000h 3effffh 3e0fffh 61 991 . . . . . . . . . 976 3df000h 3d0000h 3dffffh 3d0fffh 60 975 . . . . . . . . . 960 3cf000h 3c0000h 3cffffh 3c0fffh 59 959 . . . . . . . . . 944 3bf000h 3b0000h 3bffffh 3b0fffh 58 943 . . . . . . . . . 928 3af000h 3a0000h 3affffh 3a0fffh 57 927 . . . . . . . . . 912 39f000h 390000h 39ffffh 390fffh 56 911 . . . . . . . . . 896 38f000h 380000h 38ffffh 380fffh 55 895 . . . . . . . . . 880 37f000h 370000h 37ffffh 370fffh 54 879 . . . . . . . . . 864 36f000h 360000h 36ffffh 360fffh 53 863 . . . . . . . . . 848 35f000h 350000h 35ffffh 350fffh 52 847 . . . . . . . . . 832 34f000h 340000h 34ffffh 340fffh 51 831 . . . . . . . . . 816 33f000h 330000h 33ffffh 330fffh 50 815 . . . . . . . . . 800 32f000h 320000h 32ffffh 320fffh 49 799 . . . . . . . . . 784 31f000h 310000h 31ffffh 310fffh 48 783 . . . . . . . . . 768 30f000h 300000h 30ffffh 300fffh block 47 767 . . . . . . . . . 752 2ff000h 2f0000h 2fffffh 2f0fffh sector address range 46 751 . . . . . . . . . 736 2ef000h 2e0000h 2effffh 2e0fffh 45 735 . . . . . . . . . 720 2df000h 2d0000h 2dffffh 2d0fffh 44 719 . . . . . . . . . 704 2cf000h 2c0000h 2cffffh 2c0fffh 43 703 . . . . . . . . . 688 2bf000h 2b0000h 2bffffh 2b0fffh 42 687 . . . . . . . . . 672 2af000h 2a0000h 2affffh 2a0fffh 41 671 . . . . . . . . . 656 29f000h 290000h 29ffffh 290fffh 40 655 . . . . . . . . . 640 28f000h 280000h 28ffffh 280fffh 39 639 . . . . . . . . . 624 27f000h 270000h 27ffffh 270fffh 38 623 . . . . . . . . . 608 26f000h 260000h 26ffffh 260fffh 37 607 . . . . . . . . . 592 25f000h 250000h 25ffffh 250fffh 36 591 . . . . . . . . . 576 24f000h 240000h 24ffffh 240fffh 35 575 . . . . . . . . . 560 23f000h 230000h 23ffffh 230fffh 34 559 . . . . . . . . . 544 22f000h 220000h 22ffffh 220fffh 33 543 . . . . . . . . . 528 21f000h 210000h 21ffffh 210fffh 32 527 . . . . . . . . . 512 20f000h 200000h 20ffffh 200fffh
16 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 block 31 511 . . . . . . . . . 496 1ff000h 1f0000h 1fffffh 1f0fffh sector address range 30 495 . . . . . . . . . 480 1ef000h 1e0000h 1effffh 1e0fffh 29 479 . . . . . . . . . 464 1df000h 1d0000h 1dffffh 1d0fffh 28 463 . . . . . . . . . 448 1cf000h 1c0000h 1cffffh 1c0fffh 27 447 . . . . . . . . . 432 1bf000h 1b0000h 1bffffh 1b0fffh 26 431 . . . . . . . . . 416 1af000h 1a0000h 1affffh 1a0fffh 25 415 . . . . . . . . . 400 19f000h 190000h 19ffffh 190fffh 24 399 . . . . . . . . . 384 18f000h 180000h 18ffffh 180fffh 23 383 . . . . . . . . . 368 17f000h 170000h 17ffffh 170fffh 22 367 . . . . . . . . . 352 16f000h 160000h 16ffffh 160fffh 21 351 . . . . . . . . . 336 15f000h 150000h 15ffffh 150fffh 20 335 . . . . . . . . . 320 14f000h 140000h 14ffffh 140fffh 19 319 . . . . . . . . . 304 13f000h 130000h 13ffffh 130fffh 18 303 . . . . . . . . . 288 12f000h 120000h 12ffffh 120fffh 17 287 . . . . . . . . . 272 11f000h 110000h 11ffffh 110fffh 16 271 . . . . . . . . . 256 10f000h 100000h 10ffffh 100fffh block 15 255 . . . . . . . . . 240 0ff000h 0f0000h 0fffffh 0f0fffh sector address range 14 239 . . . . . . . . . 224 0ef000h 0e0000h 0effffh 0e0fffh 13 223 . . . . . . . . . 208 0df000h 0d0000h 0dffffh 0d0fffh 12 207 . . . . . . . . . 192 0cf000h 0c0000h 0cffffh 0c0fffh 11 191 . . . . . . . . . 176 0bf000h 0b0000h 0bffffh 0b0fffh 10 175 . . . . . . . . . 160 0af000h 0a0000h 0affffh 0a0fffh 9 159 . . . . . . . . . 144 09f000h 090000h 09ffffh 090fffh 8 143 . . . . . . . . . 128 08f000h 080000h 08ffffh 080fffh 7 127 . . . . . . . . . 112 07f000h 070000h 07ffffh 070fffh 6 111 . . . . . . . . . 96 06f000h 060000h 06ffffh 060fffh 5 95 . . . . . . . . . 80 05f000h 050000h 05ffffh 050fffh 4 79 . . . . . . . . . 64 04f000h 040000h 04ffffh 040fffh 3 63 . . . . . . . . . 48 03f000h 030000h 03ffffh 030fffh 2 47 . . . . . . . . . 32 02f000h 020000h 02ffffh 020fffh 1 31 . . . . . . . . . 16 01f000h 010000h 01ffffh 010fffh 0 15 . . . . . . . . . 4 00f000h 004000h 00ffffh 004fffh 3 003000h 003fffh 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh
17 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, so pin of this lsi should be high-z. 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock(sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as figure 3. figure 3. serial modes supported 5. for the following instructions: rdid, rdsr, rdscur, read, fast_read, 2read, res, rems and rems2 the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be, ce, pp, cp, rdp, dp, enso, exso,and wrscur, the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of write status register, program, erase operation, to access the memory array is neglected and not affect the current operation of write status register, program, erase. note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. sclk msb cpha si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb
18 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 command description (1) write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, cp, se, be, ce, and wrsr, which are intended to change the device content, should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes low-> sending wren instruction code-> cs# goes high. (see figure 12) (2) write disable (wrdi) the write disable (wrdi) instruction is for resetting write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes low-> sending wrdi instruction code-> cs# goes high. (see figure 13) the wel bit is reset by following situations: - power-up - write disable (wrdi) instruction completion - write status register (wrsr) instruction completion - page program (pp) instruction completion - sector erase (se) instruction completion - block erase (be) instruction completion - chip erase (ce) instruction completion - continuously program mode (cp) instruction completion (3) read identification (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the mxic manufacturer id is c2(hex), the memory type id is 20(hex) as the first-byte device id, and the individual device id of second-byte id are listed as table of "id definitions". the sequence of issuing rdid instruction is: cs# goes low-> sending rdid instruction code -> 24-bits id data out on so -> to end rdid operation can use cs# to high at any time during data out. (see figure. 14) while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage.
19 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 (4) read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: cs# goes low-> sending rdsr instruction code-> status register data out on so (see figure. 15) the definition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. the program/erase command will be ignored and not affect value of wel bit if it is applied to a protected memory area. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3, bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits define the protected area of the memory to against page program (pp), sector erase (se), block erase (be) and chip erase(ce) instructions (only if all block protect bits set to 0, the ce instruction can be executed). continuously program mode( cp mode) bit. the continuously program mode bit indicates the status of cp mode, "0" indicates not in cp mode; "1" indicates in cp mode. srwd bit. the status register write disable (srwd) bit, non-volatile bit, is operated together with write protection (wp#/ acc) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp#/acc pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3, bp2, bp1, bp0) are read only. status register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write p rotect ) continuously program mode ( cp mode ) bp3 (level of p rotected block ) bp2 (level of p rotected block ) bp1 (level of p rotected block ) bp0 (level of p rotected block ) wel (write enable latch ) wip (write in p ro g ress bit ) 1= status register write disable 0 = normal program mode 1 = cp mode(default 0) (note1) (note1) (note1) (note1) 1= write enable 0= not write enable 1= writ e operation 0= not in write operation non- volatile bit volatile bit non- volatile bit non- volatile bit non- volatile bit non- volatile bit volatile bit volatile bit note1: see the table "protected area sizes"
20 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 (5) write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in advance. the wrsr instruction can change the value of block protect (bp3, bp2, bp1, bp0) bits to define the protected area of memory (as shown in table 1). the wrsr also can set or reset the status register write disable (srwd) bit in accordance with write protection (wp#/acc) pin signal. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: cs# goes low-> sending wrsr instruction code-> status register data on si-> cs# goes high. (see figure 16) the wrsr instruction has no effect on b6, b1, b0 of the status register. the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self- timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. table 6. protection modes note: 1. as defined by the values in the block protect (bp3, bp2, bp1, bp0) bits of the status register, as shown in table 1. as the above table showing, the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when srwd bit=0, no matter wp#/acc is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defined by bp3, bp2, bp1, bp0, is at software protected mode (spm). - when srwd bit=1 and wp#/acc is high, the wren instruction may set the wel bit can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defined by bp3, bp2, bp1, bp0, is at software protected mode (spm) mode status register condition software protection mode(spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp3 bits can be changed wp# and srwd bit status memory wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. the protected area cannot be program or erase. wp#=0, srwd bit=1 the srwd, bp0-bp3 of status register bits cannot be changed hardware protection mode (hpm)
21 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 note: if srwd bit=1 but wp#/acc is low, it is impossible to write the status register even if the wel bit has previously been set. it is rejected to write the status register and not be executed. hardware protected mode (hpm): - when srwd bit=1, and then wp#/acc is low (or wp#/acc is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp3, bp2, bp1, bp0 and hardware protected mode by the wp#/acc to against data modification. note: to exit the hardware protected mode requires wp#/acc driving high once the hardware protected mode is entered. if the wp#/acc pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp3, bp2, bp1, bp0. (6) read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes low-> sending read instruction code-> 3-byte address on si -> data out on so-> to end read operation can use cs# to high at any time during data out. (see figure. 17) (7) read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fast_read instruction is: cs# goes low-> sending fast_read instruction code-> 3-byte address on si-> 1-dummy byte address on si->data out on so-> to end fast_read operation can use cs# to high at any time during data out. (see figure. 18) while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any impact on the program/erase/write status register current cycle. (8) 2 x i/o read mode (2read) the 2read instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits(interleave on 2 i/o pins) shift out on the falling edge of sclk at a maximum frequency ft. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 2read instruction, the following address/dummy/ data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing 2read instruction is: cs# goes low sending 2read instruction 24-bit address interleave on sio1 & sio0 8-bit dummy interleave on sio1 & sio0 data out interleave on sio1 & sio0 to end 2read operation can use cs# to high at any time during data out (see figure of 2 x i/o read mode timing waveform)
22 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 while program/erase/write status register cycle is in progress, 2read instruction is rejected without any impact on the program/erase/write status register current cycle. the 2 i/o only perform read operation. program/erase /read id/read status/read id....operation do not support 2 i/o throughputs. (9) sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see table 3) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most significant address) select the sector address. the sequence of issuing se instruction is: cs# goes low -> sending se instruction code-> 3-byte address on si -> cs# goes high. (see figure 22) the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the sector erase (se) instruction will not be executed on the page. (10) block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k- byte sector erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (see table 3) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low -> sending be instruction code-> 3-byte address on si -> cs# goes high. (see figure 23) the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the block erase (be) instruction will not be executed on the page. (11) chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the chip erase (ce). any address of the sector (see table 3) is a valid address for chip erase (ce) instruction. the cs# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes low-> sending ce instruction code-> cs# goes high. (see figure 24)
23 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the chip erase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected by bp3, bp2, bp1, bp0 bits, the chip erase (ce) instruction will not be executed. it will be only executed when bp3, bp2, bp1, bp0 all set to "0". (12) page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). if the eight least significant address bits (a7-a0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed from the start address if the same page (from the address whose 8 least significant address bits (a7-a0) are all 0). the cs# must keep during the whole page program cycle. the cs# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. if more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. if less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page. the sequence of issuing pp instruction is: cs# goes low-> sending pp instruction code-> 3-byte address on si-> at least 1-byte on data on si-> cs# goes high. (see figure 20) the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the page program (pp) instruction will not be executed. (13) continuously program mode (cp mode) the cp mode may enhance program performance by automatically increasing address to the next higher address after each byte data has been programmed. the continuously program (cp) instruction is for multiple byte program to flash. a write enable (wren) instruction must execute to set the write enable latch(wel) bit before sending the continuously program (cp) instruction. cs# requires to go high before cp instruction is executing. after cp instruction and address input, two bytes of data is input sequentially from msb(bit7) to lsb(bit0). the first byte data will be programmed to the initial address range with a0=0 and second byte data with a0=1. if only one byte data is input, the cp mode will not process. if more than two bytes data are input, the additional data will be ignored and only two byte data are valid. the cp program instruction will be ignored and not affect the wel bit if it is applied to a protected memory area. any byte to be programmed should be in the erase state (ff) first. it will not roll over during the cp mode, once the last unprotected address has been reached, the chip will exit cp mode and reset write enable latch bit (wel) as "0" and cp mode bit as "0". please check the wip bit status if it is not in write progress before entering next valid instruction. during cp mode, the valid commands are cp command (ad hex), wrdi command (04 hex), rdsr command (05 hex), rdpr command (a1 hex), and rdscur command (2b hex). and the wrdi command is valid after completion of a cp programming cycle, which means the wip bit=0. the sequence of issuing cp instruction is : cs# high to low-> sending cp instruction code-> 3-byte address on si-> data byte on si->cs# goes high to low-> sending cp instruction......-> last desired byte programmed or sending write disable (wrdi) instruction to end cp mode-> sending rdsr instruction to verify if cp mode is ended. (see figure of cp mode timing waveform) three methods to detect the completion of a program cycle during cp mode: 1) software method-i: by checking wip bit of status register to detect the completion of cp mode.
24 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 2) software method-ii: by waiting for a tbp time out to determine if it may load next valid command or not. 3) hardware method: by writing esry (enable so to output ry/by#) instruction to detect the completion of a program cycle during cp mode. the esry instruction must be executed before cp mode execution. once it is enable in cp mode, the cs# goes low will drive out the ry/by# status on so, "0" indicates busy stage, "1" indicates ready stage, so pin outputs tri-state if cs# goes high. dsry (disable so to output ry/by#) instruction to disable the so to output ry/by# and return to status register data output during cp mode. please note that the esry/dsry command are not accepted unless the completion of cp mode. (14) deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consumption (to entering the deep power-down mode), the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not active and all write/ program/erase instruction are ignored. when cs# goes high, it's only in standby mode not deep power-down mode. it's different from standby mode. the sequence of issuing dp instruction is: cs# goes low-> sending dp instruction code-> cs# goes high. (see figure 25) once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction. (those instructions allow the id being reading out). when power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode and reducing the current to isb2. (15) release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power- down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specified in table 6. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id definitions. this is not the same as rdid instruction. it is not recommended to use for new design. for new design, please use rdid instruction. even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. the sequence is shown as figure 26,27. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeatedly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power- down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. the rdp instruction is for releasing from deep power down mode.
25 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 table 7. id definitions (16) read electronic manufacturer id & device id (rems), (rems2) the rems & rems2 instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the rems & rems2 instruction is very similar to the release from power-down/device id instruction. the instruction is initiated by driving the cs# pin low and shift the instruction code "90h" or "efh" followed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id for mxic (c2h) and the device id are shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure 25. the device id values are listed in table of id definitions. if the one-byte address is initially set to 01h, then the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. (17) enter secured otp (enso) the enso instruction is for entering the additional 512-bit secured otp mode. the additional 512-bit secured otp is independent from main array, which may use to store unique serial number for system identifier. after entering the secured otp mode, and then follow standard read or program, procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: cs# goes low-> sending enso instruction to enter secured otp mode -> cs# goes high. please note that wrsr/wrscur commands are not acceptable during the access of secure otp region, once security otp is lock down, only read related commands are valid. (18) exit secured otp (exso) the exso instruction is for exiting the additional 512-bit secured otp mode. the sequence of issuing exso instruction is: cs# goes low-> sending exso instruction to exit secured otp mode-> cs# goes high. command t yp e manufacturer id memor y t yp e memory density c2 20 15 m anufacturer id device id c2 14 MX25L1605D rems/rems2 res rdid (jedec id) electronic id 14 electronic id 15 electronic id 16 manufacturer id memor y t yp e memory density c2 20 16 m anufacturer id device id c2 15 mx25l3205d manufacturer id memor y t yp e memory density c2 20 17 m anufacturer id device id c2 16 mx25l6405d
26 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 (19) read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence of issuing rdscur instruction is : cs# goes low-> send ing rdscur instruction -> security register data out on so-> cs# goes high. the definition of the security register bits is as below: secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory before ex- factory or not. when it is "0", it indicates non- factory lock; "1" indicates factory- lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for customer lock- down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 512-bit secured otp area cannot be update any more. while it is in 512-bit secured otp mode, array access is not allowed. table 8. security register definition (20) write security register (wrscur) the wrscur instruction is for changing the values of security register bits. unlike write status register, the wren instruction is not required before sending wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 512-bit secured otp area. once the ldso bit is set to "1", the secured otp area cannot be updated any more. the sequence of issuing wrscur instruction is :cs# goes low-> sending wrscur instruction -> cs# goes high. the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. bit7 bit6 bit5 bit4 bit3 bit1 bit0 xxxxx ldso (indicate if lock-down secrured otp indicator bit reserved reserved reserved reserved reserved reserved 0 = not lock- down 1 = lock-down (cannot program/erase otp) 0 = non- factory lock 1 = factory lock volatile bit volatile bit volatile bit volatile bit volatile bit bit2 x volatile bit non-volatile bit non-volatile bit
27 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 power-on state the device is at below states when power-up: - standby mode ( please note it is not deep power-down mode) - write enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power-up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. when vcc is lower than vwi (por threshold voltage value), the internal logic is reset and the flash device has no response to any command. for further protection on the device, after vcc reaching the vwi level, a tpuw time delay is required before the device is fully accessible for commands like write enable(wren), page program (pp), continuously program (cp), sector erase(se), chip erase(ce), wrscur and write status register(wrsr). if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the write, erase, and program command should be sent after the below time delay: - tpuw after vcc reached vwi level - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl, even time of tpuw has not passed. please refer to the figure of "power-up timing". note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uf) - at power-down stage, the vcc drops below vwi level, all operations are disable and device has no response to any command. the data corruption might occur during the stage while a write, program, erase cycle is in progress.
28 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 notice: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifications contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot vss to -2.0v and vcc to +2.0v for periods up to 20ns, see figure 4, 5. rating value ambient operating temperature -40 c to 85 c for industrial grade storage temperature -55 c to 125 c applied input voltage -0.5v to 4.6v applied output voltage -0.5v to 4.6v vcc to ground potential -0.5v to 4.6v absolute maximum ratings electrical specifications capacitance ta = 25 c, f = 1.0 mhz symbol parameter min. typ max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v figure 4.maximum negative overshoot waveform figure 5. maximum positive overshoot waveform vss vss - 2.0v 20ns 20ns 20ns vcc + 2.0v vcc 20ns 20ns 20ns
29 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 figure 6. input test waveforms and measurement level figure 7. output loading ac measurement level input timing referance level output timing referance level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v cl=30pf including jig capacitance (cl=15pf including jig capacitance for 86mhz and 50mhz@2x i/o)
30 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 symbol parameter notes min. typ max. units test conditions ili input load 1 2 ua vcc = vcc max current vin = vcc or gnd ilo output leakage 1 2 ua vcc = vcc max current vin = vcc or gnd ilihv hv pin input leakage 35 ua wp#/acc=10.5v current isb1 vcc standby 1 20 ua vin = vcc or gnd current cs# = vcc isb2 deep power-down 20 ua vin = vcc or gnd current cs# = vcc icc1 vcc read 1 25 ma f=86mhz ft=50mhz (2 x i/o read) sclk=0.1vcc/0.9vcc, so=open 20 ma f=66mhz sclk=0.1vcc/0.9vcc, so=open 10 ma f=33mhz sclk=0.1vcc/0.9vcc, so=open icc2 vcc program 1 20 m a program in progress current (pp) cs# = vcc icc3 vcc write status 20 ma program status register in progress register (wrsr) cs#=vcc current icc4 vcc sector erase 1 20 ma erase in progress current (se) cs#=vcc icc5 vcc chip erase 1 20 ma erase in progress current (ce) cs#=vcc vhh voltage for acc program/ 9.5 10.5 v vcc=2.7v~3.6v erase acceleration vil input low voltage -0.5 0.3vcc v vih input high voltage 0.7vcc vcc+0.4 v vol output low voltage 0.4 v iol = 1.6ma voh output high voltage vcc-0.2 v ioh = -100ua table 9. dc characteristics (temperature = -40 c to 85 c for industrial grade, vcc = 2.7v ~ 3.6v)
31 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 table 10. ac characteristics (temperature = -40 c to 85 c for industrial grade, vcc = 2.7v ~ 3.6v) symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: 10khz 86 mhz fast_read, pp, se, be, ce, dp, res,rdp (condition:15pf) wren, wrdi, rdid, rdsr, wrsr 66 mhz (condition:30pf) frsclk fr clock frequency for read instructions 10khz 33 mhz ftsclk ft cl ock frequency for 2read instructions 10khz 50 mhz (condition:15pf) tch(1) tclh clock high time 7 ns tcl(1) tcll cl ock low time 7 ns tclch(2) clock rise time (3) (peak to peak) 0.1 v/ns tchcl(2) cl ock fall time (3) (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 5 ns tchsl cs# not active hold time (relative to sclk) 5 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 5 ns tchsh cs# active hold time (relative to sclk) 5 ns tshch cs# not active setup time (relative to sclk) 5 ns tshsl tcsh cs# deselect time 100 ns tshqz(2) tdis output disable time 64mb/ 2.7v-3.6v 10 ns 32mb/ 3.0v-3.6v 8 ns 16mb tclqv tv clock low to output valid 64mb/ 2.7v-3.6v 10 ns 32mb/ 3.0v-3.6v 8 ns 16mb tclqx tho output hold time 0 ns thlch hold# setup time (relative to sclk) 5 ns tchhh hold# hold time (relative to sclk) 5 ns thhch hold setup time (relative to sclk) 5 ns tchhl hold hold time (relative to sclk) 5 ns thhqx(2) tlz hold to output low-z 64mb/ 2.7v-3.6v 10 ns 32mb/ 3.0v-3.6v 8 ns 16mb thlqz(2) thz ho ld# to output high-z 64mb/ 2.7v-3.6v 10 ns 32mb/ 3.0v-3.6v 8 ns 16mb twhsl(4) w rite protect setup time 20 ns tshwl(4) write protect hold time 100 ns tdp(2) cs# high to deep power-down mode 10 us tres1(2) cs# high to standby mode without electronic signature read 8.8 us tres2(2) cs# high to standby mode with electronic signature read 8.8 us
32 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 symbol alt. parameter min. typ. max. unit tw write status register cycle time 40 100 ms tbp byte-program 9 300 us tpp page program cycle time 1.4 5 ms tse sector erase cycle time 60 300 ms tbe block erase cycle time 0.7 2 s tce chip erase cycle time 64mb 50 80 s 32mb 25 50 s 16mb 14 30 s notes: 1. tch + tcl must be greater than or equal to 1/ fc. for fast read, tcl/tch=5.5/5.5. 2. value guaranteed by characterization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1. 5. test condition is shown as figure 6.
33 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low 200 us tpuw(1) time delay to write instruction 1 10 ms vwi(1) write inhibit voltage 1.5 2.5 v initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). note: 1. these parameters are characterized only. table 11. power-up timing and vwi threshold
34 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 figure 8. serial input timing sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl figure 9. output timing lsb addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv sclk so cs# si
35 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 figure 10. hold timing tchhl thlch thhch tchhh thhqx thlqz sclk so cs# hold# * si is "don't care" during hold operation. figure 11. wp# disable setup and hold timing during wrsr when srwd=1 high-z 01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so
36 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 figure 12. write enable (wren) sequence (command 06) figure 13. write disable (wrdi) sequence (command 04) figure 14. read identification (rdid) sequence (command 9f) 2 1 3456789101112131415 command 0 manufacturer identification high-z msb 15 1413 3210 device identification msb 765 3210 16 17 18 28 29 30 31 sclk si cs# so 9f 2 1 34567 high-z 0 06 command sclk si cs# so 2 1 34567 high-z 0 04 command sclk si cs# so
37 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 figure 15. read status register (rdsr) sequence (command 05) figure 16. write status register (wrsr) sequence (command 01) figure 17. read data bytes (read) sequence (command 03) 2 1 3456789101112131415 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05 2 1 3456789101112131415 status register in 0 765432 0 1 msb sclk si cs# so 01 high-z command sclk si cs# so 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 data out 1 24-bit address 0 msb msb 2 39 data out 2 03 high-z command
38 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 figure 18. read at higher speed (fast_read) sequence (command 0b) 23 2 1 345678910 28293031 2221 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35 sclk si cs# so sclk si cs# so 0b command
39 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 figure 19. 2 x i/o read mode sequence (command bb) high impedance 2 1 345678 0 sclk si/sio0 so/sio1 cs# 91011 181920 bb(hex) dummy dummy address bit22, bit20, bit18...bit0 data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... address bit23, bit21, bit19...bit1 21 22 23 24 25 26 27 figure 20. page program (pp) sequence (command 02) 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 765432 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02 command
40 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 figure 22. sector erase (se) sequence (command 20) figure 23. block erase (be) sequence (command d8) figure 21. continously program (cp) mode sequence with hardware detection (command ad) note: (1) during cp mode, the valid commands are cp command (ad hex), wrdi command (04 hex), rdsr command (05 hex), rdpr command (a1 hex), and rdscur command (2b hex). (2) once an internal programming operation begins, cs# goes low will drive the status on the so pin and cs# goes high will return the so pin to tri-state. (3) to end the cp mode, either reaching the highest unprotected address or sending write disable (wrdi) command (04 hex) may achieve it and then it is recommended to send rdsr command (05 hex) to verify if cp mode is ended note: se command is 20(hex). note: be command is d8(hex). 24 bit address 2 1 3456789 293031 0 23 22 2 0 1 msb sclk cs# si d8 command cs# sclk 01 6 789 si command ad (hex) 30 31 31 s0 high impedance 32 47 48 status (2) data in 24-bit address byte 0, byte1 01 valid command (1) data in byte n-1, byte n 678 20 21 22 23 0 04 (hex) 24 7 0 7 05 (hex) 8 24 bit address 2 1 3456789 293031 0 23 22 2 1 0 msb sclk cs# si 20 command
41 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 figure 24. chip erase (ce) sequence (command 60 or c7) figure 25. deep power-down (dp) sequence (command b9) figure 26. release from deep power-down and read electronic signature (res) sequence (command ab) note: ce command is 60(hex) or c7(hex). 2 1 34567 0 60 or c7 sclk si cs# command 2 1 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9 command 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 765432 0 1 high-z electronic signature out 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so ab command
42 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 notes: (1) add=00h will output the manufacturer's id first and add=01h will output device id first (2) instruction is either 90(hex) or ef(hex). figure 27. release from deep power-down (rdp) sequence (command ab) figure 28. read electronic manufacturer & device id (rems) sequence (command 90 or ef) 15 14 13 3 2 1 0 2 1 345678910 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 manufacturer id add (1) msb 7 6543210 device id msb msb 7 47 765432 0 1 35 31 30 29 28 sclk si cs# so sclk si cs# so x 90 high-z command 2 1 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so ab command
43 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 figure 29. power-up timing v cc v cc (min) v wi reset state of the flash chip selection is not allowed program, erase and write commands are ignored tvsl tpuw time read command is allowed device is fully accessible v cc (max) note: vcc (max.) is 3.6v and vcc (min.) is 2.7v.
44 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 recommended operating conditions at device power-up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a. ac timing at device power-up notes : 1. sampled, not 100% tested. 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the figure, please refer to "ac characteristics" table. symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd
45 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 erase and programming performance parameter min. typ. (1) max. (2) unit write status register cycle time 40 100 ms sector erase time 60 300 ms block erase time 0.7 2 s 64mb 50 80 s chip erase time 32mb 25 50 s 16mb 14 30 s 64mb 30 48 s chip erase time (at acc mode) 32mb 15 30 s 16mb 8 18 s byte program time (via page program command) 9 300 us page program time 1.4 5 ms page program time (at acc mode) 1.4 5 ms erase/program cycle 100,000 cycles note: 1. typical program and erase time assumes the following conditions: 25 c, 3.3v, and checker board pattern. 2. under worst conditions of 85 c and 2.7v. 3. system-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4. erase/program cycles comply with jedec jesd-47e & a117a standard. min. max. input voltage with respect to gnd on acc -1.0v 10.5v input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. latch-up characteristics
46 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 ordering information part no. clock operating standby temperature package remark (mhz) current max. current max. (ma) (ua) MX25L1605Dm2i-12g 86 25 20 -40 c~85 c 8-sop pb-free (200mil) MX25L1605Dmi-12g 86 25 20 -40 c~85 c 16-sop pb-free MX25L1605Dm1i-12g 86 25 20 -40 c~85 c 8-sop pb-free (150mil) MX25L1605Dpi-12g 86 25 20 -40 c~85 c 8-pdip pb-free (300mil) MX25L1605Dzni-12g 86 25 20 -40 c~85 c 8-wson pb-free (6x5mm) MX25L1605Dzui-12g 86 25 20 -40 c~85 c 8-uson pb-free (4x4mm) mx25l3205dzni-12g 86 25 20 -40 c~85 c 8-wson pb-free (6x5mm) mx25l3205dm2i-12g 86 25 20 -40 c~85 c 8-sop pb-free (200mil) mx25l3205dmi-12g 86 25 20 -40 c~85 c 16-sop pb-free mx25l3205dpi-12g 86 25 20 -40 c~85 c 8-pdip pb-free (300mil) mx25l3205dzui-12g 86 25 20 -40 c~85 c 8-uson pb-free (4x4mm) mx25l6405dzni-12g 86 25 20 -40 c~85 c 8-wson pb-free (8x6mm) mx25l6405dmi-12g 86 25 20 -40 c~85 c 16-sop pb-free
47 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 part name description mx 25 l 12 zn i g option: g: pb-free speed: 12: 86mhz temperature range: i: industrial (-40?c to 85?c) package: zn: wson (0.8mm package height) zu: uson (0.6mm package height) m: 300mil 16-sop m1: 150mil 8-sop m2: 200mil 8-sop p: 300mil 8-pdip density & mode: 1605d: 16mb 3205d: 32mb 6405d: 64mb type: l: 3v device: 25: serial flash 1605d
48 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 package information
49 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008
50 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008
51 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008
52 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008
53 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008
54 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008
55 MX25L1605D mx25l3205d mx25l6405d p/n: pm1290 rev. 1.4, oct. 01, 2008 revision history revision no. description page date 1.0 1. removed "preliminary" p1 mar/07/2008 1.1 1. dual i/o pre-released p1,3,21,31 may/12/2008 1.2 1. added 8-land uson package information p2,4,46,47,50 jul/08/2008 1.3 1. modified figure 4 & 5 waveform p28 aug/15/2008 2. revised vhh spec from 11.0v(typ.)~11.5v(max.) to p4,8,30,45 9.5v(min.)~10.5v(max.) 1.4 1. revised sector erase time spec from 90ms(typ.) to 60ms(typ.) p32,45 oct/01/2008 2. removed "advanced information" for mx25l3205dzui-12g p46
MX25L1605D mx25l3205d mx25l6405d 56 m acronix i nternational c o., l td . headquarters macronix, int'l co., ltd. 16, li-hsin road, science park, hsinchu, taiwan, r.o.c. tel: +886-3-5786688 fax: +886-3-5632888 macronix america, inc. 680 north mccarthy blvd. milpitas, ca 95035, u.s.a. tel: +1-408-262-8887 fax: +1-408-262-8810 email: sales.northamerica@macronix.com macronix asia limited. nkf bldg. 5f, 1-2 higashida-cho, kawasaki-ku kawasaki-shi, kanagawa pref. 210-0005, japan tel: +81-44-246-9100 fax: +81-44-246-9105 macronix (hong kong) co., limited. 702-703, 7/f, building 9, hong kong science park, 5 science park west avenue, sha tin, n.t. tel: +86-852-2607-4289 fax: +86-852-2607-4229 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. taipei office macronix, int'l co., ltd. 19f, 4, min-chuan e. road, sec. 3, taipei, taiwan, r.o.c. tel: +886-2-2509-3300 fax: +886-2-2509-2200 macronix europe n.v. koningin astridlaan 59, bus 1 1780 wemmel belgium tel: +32-2-456-8020 fax: +32-2-456-8021 singapore office macronix pte. ltd. 1 marine parade central #11-03 parkway centre singapore 449408 tel: +65-6346-5505 fax: +65-6348-8096 macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications.


▲Up To Search▲   

 
Price & Availability of MX25L1605D

All Rights Reserved © IC-ON-LINE 2003 - 2022  
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]
 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X